Page 105 - 49A Field Guide to Genetic Programming

10.4 Running GP on Parallel Hardware 91

Blocks bit the

8. 6×64 banks, 2007).
of
Thread Processor The
SP SP SP SP TA TF TF L1 L2 CACHE 32bits blocks memory (nVidia,
SP SP SP SP TA TF TF memory 64 MB Filters.
SP SP SP SP TA TF TF L1 32bits 64 MB 16
SP SP SP SP TA TF TF ROP in off-chip
SP SP SP SP TA TF TF L1 arranged Texture six Partitions.
SP SP SP SP TA TF TF 8
SP SP SP SP TA TF TF L1 L2 CACHE 32bits the
memory are of
SP SP SP SP TA TF TF 64 MB and
SP SP SP SP TA TF TF L1 ROP 32bits 64 MB units each Operation
SP SP SP SP TA TF TF
SP SP SP SP TA TF TF L1 Processors for
SP SP SP SP TA TF TF L2 CACHE Address Raster

SP SP SP SP TA TF TF L1 32bits 64 MB chips 6
SP SP SP SP SP SP SP SP TA TA TF TF TF TF ROP memory 32bits 64 MB Stream Texture two are
Thread Execution Manager SP SP SP SP SP SP SP SP TA TA TF TF TF TF L1 L1 MHz 4 are there There

SP SP SP SP SP SP SP SP TA TA TF TF TF TF L1 L2 CACHE memory 32bits 64 MB 1360 cache, bank.)
SP SP SP SP TA TF TF 32bits 64 MB 128 L1 (Since
ROP per
SP SP SP SP TA TF TF L1 The KB
SP SP SP SP TA TF TF MHz. Mhz
SP SP SP SP TA TF TF L1 8/1
SP SP SP SP TA TF TF L2 CACHE 32bits 64 MB diagram. an 900 1800
SP SP SP SP TA TF TF L1 memory 32bits 64 MB at to
PCI Express SP SP SP SP SP SP SP SP TA TA TF TF TF TF ROP Block shown), RAM up

PC Input Assembler SP SP SP SP TA TF TF L1 8800 (not chip at

SP SP SP SP SP SP SP SP TA TA TF TF TF TF L1 L2 CACHE 32bits 64 MB off running
SP SP SP SP TA TF TF memory 32bits nVidia memory
SP SP SP SP TA TF TF L1 ROP 64 MB links
10.1: KB (dashed) effectively

Figure 16 share bus is bus