Page 83 - slides.dvi

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–
–
if
–
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at
Some
Operating
Recall:
after
line
mode
interrupt
end
to
resume
jump
saves
saves
is
Systems
multiple
more
hardware
of
—
Interrupts
changes
to
a
I/O
where
levels
handle
each
dependent
asserted
program
of
well
we
complex
processor
mechanism:
vectoring
Subsystem
processor
left
of
then
Revisited
interrupt-handling
known
mismatch
status,
off.
registers
counter,
instruction,
mode,
interrupts
processors
routine
and
interrupts
address
processor:
between
is
(or
processor
provide:
CPU
its
finished,
and
checks
can
contents)
device
use
interrupt
e.g.
speeds,
the
line(s)
for
rti
processors
pending
instruction
provide
to
an
interrupt
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